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PD - 95043
IRLI3215PBF
HEXFET(R) Power MOSFET
l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free
D
VDSS = 150V RDS(on) = 0.166
G S
ID = 12A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing.
TO-220 FULLP AK
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew
Max.
12 8.5 48 80 0.53 16 130 7.2 8.0 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient
Typ.
--- ---
Max.
1.9 65
Units
C/W
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1
2/24/04
IRLI3215PBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Min. Typ. Max. Units Conditions 150 --- --- V VGS = 0V, ID = 250A --- 0.20 --- V/C Reference to 25C, ID = 1mA --- --- 0.166 VGS = 10V, ID = 7.2A --- --- 0.184 VGS = 5.0V, ID = 7.2A --- --- 0.208 VGS = 4.0V, ID = 6A 1.0 --- 2.0 V VDS = VGS, ID = 250A 8.3 --- --- S VDS = 25V, ID = 7.2A --- --- 25 VDS = 150V, VGS = 0V A --- --- 250 VDS = 120V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 35 ID = 7.2A --- --- 4.1 nC VDS = 120V --- --- 21 VGS = 5.0V, See Fig. 6 and 13 --- 7.4 --- VDD = 75V --- 45 --- ID = 7.2A ns --- 38 --- RG = 12, VGS = 5.0V --- 36 --- RD = 10.2, See Fig. 10 Between lead, 4.5 nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 775 --- VGS = 0V --- 140 --- pF VDS = 25V --- 70 --- = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Q rr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 12 showing the A G integral reverse --- --- 48 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 7.2A, VGS = 0V --- 160 240 ns TJ = 25C, IF = 7.2A --- 810 1210 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) Starting TJ = 25C, L = 4.9mH RG = 25, IAS = 7.2A. (See Figure 12) ISD 7.2A, di/dt 100A/s, VDD V(BR)DSS, TJ 175C
Pulse width 300s; duty cycle 2%. Caculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4. Uses IRL3215 data and test conditions.
2
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IRLI3215PBF
10
VGS VGS 15V 15V 10V 10V 8.0V 5V 7.0V 4.5V 6.0V 3.5V 5.5V 3V 5.0V 2.75V BOTTOM 2.50V BOTTOM 4.5V TOP TOP
10
I D , Drain-to-Source Current (A)
1
I D , Drain-to-Source Current (A)
1
VGS VGS 15V 15V 10V 10V 8.0V 5V 7.0V 4.5V 6.0V 3.5V 5.5V 3V 5.0V 2.75V BOTTOM 4.5V BOTTOM 2.50V TOP TOP
2.5V
0.1
0.1
2.5V
0.01 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
0.01 0.1
20s PULSE WIDTH TJ = 175 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
10
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
TJ = 25 C
ID = 12A
I D , Drain-to-Source Current (A)
2.5
TJ = 175 C
1
2.0
1.5
1.0
0.5
0.1 2.0
V DS = 50V 20s PULSE WIDTH 3.0 4.0 5.0 6.0 7.0
0.0 -60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRLI3215PBF
2500
2000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
15
ID = 7.2 A VDS = 120V VDS = 75V VDS = 30V
C, Capacitance (pF)
10
1500
Ciss Coss Crss
1000
5
500
0
1
10
100
0
FOR TEST CIRCUIT SEE FIGURE 13
0 10 20 30 40 50
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
ID , Drain Current (A)
100 10us 10 100us 1ms 1 10ms
TJ = 175 C
1
TJ = 25 C
0.1 0.2
V GS = 0 V
0.4 0.6 0.8 1.0 1.2
0.1
TC = 25 C TJ = 175 C Single Pulse
1 10 100 1000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLI3215PBF
12
V DS VGS
RD
ID , Drain Current (A)
9
RG 10V
D.U.T.
+
-VDD
6
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
3
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1 D = 0.50 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLI3215PBF
EAS , Single Pulse Avalanche Energy (mJ)
300
TOP
250
15V
BOTTOM
ID 2.9A 5.1A 7.2A
VDS
L
DRIVER
200
RG
20V
D.U.T
IAS tp
+ V - DD
150
A
0.01
100
Fig 12a. Unclamped Inductive Test Circuit
50
0
25
50
75
100
125
150
175
V(BR)DSS tp
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS
QGD
VGS
3mA
D.U.T.
+ V - DS
VG
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLI3215PBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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IRLI3215PBF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E X AM P L E : T H IS IS AN IR F I8 4 0 G W IT H AS S E M B L Y L OT CODE 3 432 AS S E M B L E D O N W W 2 4 1 9 9 9 IN T H E AS S E M B L Y L IN E "K " IN T E R N AT IO N AL R E CT IF IE R L OGO AS S E M B L Y L OT CODE P AR T N U M B E R
IR F I8 40 G 924 K 34 32
Note: "P" in assembly line position indicates "Lead-Free"
D AT E C O D E Y E AR 9 = 1 9 9 9 WE E K 24 L IN E K
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.02/04
8
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